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I NTEGRATED C IRCUITS D IVISION
1.9 Switching Specifications
CPC5002
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Timing Specifications
Clock Frequency
Propagation Delay
Output Falling 1, 3
I SINK =6mA, C L =20pF
I F =1.5mA, V DD =3.3V,
R PU =499 ? , C L =20pF,
f MAX
t PHL
-
35
10
81
-
120
MHz
ns
Output Rising
2, 3
0.5V IN to 0.5V DD_OUT
t PLH
35
81
120
Pulse Width Distortion: |t PLH - t PLH |
As per t PHL and t PLH
PWD
85
ns
Propagation Delay Skew 3
Output Fall Time, 90% to 10%
As per t PHL and t PLH
I F =1.5mA, V DD =3.3V,
R PU =499 ? , C L =20pF
t PSK
t f
-
10
-
15
50
-
ns
ns
Common Mode Specifications
Common Mode Transient Immunity
V CM =20V P-P , V DD =3.3V, T A =25°C
V OUT = High
V OUT = Low
V OUT >2V
V OUT <0.8V
CM H
CM L
5
7
-
-
-
-
kV/ ? s
1
2
3
Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing C FWD .
Rising propagation delay depends on R PU , C L , and I F .
Increasing I F above 2 ? I TH (by reducing R S ) increases the rising propagation delay.
Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002
when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.
1.10 Propagation Delay Test Circuit
27pF
? CPC5002
V DD
3.3 V
2k Ω
I F
V OUT
R PU
499 Ω
C L
20pF
R03
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